Semiconductor module and method for forming the same

ABSTRACT

Under the present invention, a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure. The interposer structure comprises an elastomeric, compliant material that includes metallurgic through connections having a predetermined shape. In a typical embodiment, the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate. By utilizing the interposer structure in accordance with the present invention, the problems associated with previous semiconductor module designs are alleviated.

REFERENCE TO PRIOR APPLICATIONS

The current application is a continuation application of co-pending U.S.patent application Ser. No. 10/721,984, filed on 25 Nov. 2003, which ishereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a semiconductor module andmethod for forming the same. Specifically, the present inventionprovides a semiconductor module having an interposer structure withmetallurgical through connections for electrically connecting asemiconductor chip to a substrate.

2. Related Art

In the production of semiconductor modules, a semiconductor chip isoften connected to a carrier such as a substrate. Typically, theconnection is made using controlled collapse chip connection (C4)technology whereby solder bumps are used to join the two componentstogether. Unfortunately, several problems emerge with the existingtechnology. First, the semiconductor chip usually has a differentcoefficient of thermal expansion (CTE) than the substrate. Given theclose physical proximity of the semiconductor chip to the substrate, thesolder bumps often deteriorate as the module heats up and cools off.This is especially the case with larger die sizes.

In addition, ceramic substrates (if used) are generally non-planar,which can become a gating factor as the substrate X-Y dimensionsincrease. With shrinking pitch, there is a need to shrink C4 bumpdimensions to avoid nearest neighbor shorting. However, a small C4 bumpheight results in a larger percentage of variation across the grid ofbumps. Further, when the interconnections at the chip to substrate levelmigrate to a lead-free system, there will be no solder temperaturehierarchy between first and second level interconnections, thus,creating an increased strain on the C4 structure due to highertemperatures of subsequent assembly operations. Still yet, currentmethods of depositing and joining C4 interconnections are expensive andinvolve the use of specific under bump metallization (UBM), which mighthave to be customized. Also, the UBM may need additional layers such asdiffusion barriers and chip encapsulants so that it may endure a meltingor partially melting C4 structure that reacts with the UBM duringsubsequent assembly operations.

In view of the foregoing, there exists a need for an improvedsemiconductor module and method for forming the same. Specifically, aneed exists for a semiconductor chip to be electrically connected to asubstrate or the like so that the above concerns are alleviated.

SUMMARY OF THE INVENTION

In general, the present invention provides a semiconductor module andmethod for forming the same. Specifically, under the present invention,a semiconductor chip is electrically connected to a substrate (e.g.,organic, ceramic, etc.) by an interposer structure. The interposerstructure comprises an elastomeric, compliant material that includesmetallurgical through connections having a predetermined shape. In atypical embodiment, the metallurgical through connections electricallyconnect an under bump metallization of the semiconductor chip to a topsurface metallization of the substrate. By utilizing the interposerstructure in accordance with the present invention, the problemsassociated with previous semiconductor module designs are alleviated.

A first aspect of the present invention provides a semiconductor module,comprising a semiconductor chip; a substrate; and an interposerstructure electrically connecting the semiconductor chip to thesubstrate, wherein the interposer structure includes metallurgicalthrough connections having a predetermined shape.

A second aspect of the present invention provides a semiconductormodule, comprising a semiconductor chip having an under bumpmetallization; a substrate having a top surface metallization; and aninterposer structure electrically connecting the under bumpmetallization to the top surface metallization, wherein the interposerstructure comprises an elastomeric, compliant material that includesmetallurgical through connections having a predetermined shape.

A third aspect of the present invention provides a method for forming asemiconductor module, comprising: embedding metallurgical throughconnections within an elastomeric, compliant material to form aninterposer structure; and positioning the interposer structure between asemiconductor chip and a substrate to electrically connect thesemiconductor chip to the substrate.

Therefore, the present invention provides a semiconductor module andmethod for forming the same.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of this invention will be more readilyunderstood from the following detailed description of the variousaspects of the invention taken in conjunction with the accompanyingdrawings in which:

FIG. 1 depicts a semiconductor module having an interposer structure,according to the present invention.

FIG. 2 depicts the semiconductor module of FIG. 1 further including aheat spreader and a heat sink.

FIG. 3 depicts the semiconductor module of FIG. 2 further includingunderfill.

FIG. 4 depicts the semiconductor module of FIG. 3 under a Land GridArray load.

FIG. 5 depicts the semiconductor module of FIG. 1 in a TCA application.

The drawings are merely schematic representations, not intended toportray specific parameters of the invention. The drawings are intendedto depict only typical embodiments of the invention, and thereforeshould not be considered as limiting the scope of the invention. In thedrawings, like numbering represents like elements.

DETAILED DESCRIPTION OF THE INVENTION

As indicated above, the present invention provides a semiconductormodule and method for forming the same. Specifically, under the presentinvention, a semiconductor chip is electrically connected to a substrate(e.g., organic, ceramic, etc.) by an interposer structure. Theinterposer structure comprises an elastomeric, compliant material thatincludes metallurgical through connections having a predetermined shape.In a typical embodiment, the metallurgical through connectionselectrically connect an under bump metallization of the semiconductorchip to a top surface metallization of the substrate. By utilizing theinterposer structure in accordance with the present invention, theproblems associated with previous semiconductor module designs arealleviated.

Referring now to FIG. 1, an illustrative semiconductor module 10 formedin accordance with the present invention is shown. As depicted,semiconductor module 10 includes semiconductor chip 12 andcarrier/substrate 14 with interposer structure 16 positionedtherebetween. It should be appreciated in advance that semiconductormodule 10 could be a single chip module or a multi-chip module. In thecase of a multi-chip module, interposer structure 16 could be positionedbetween each semiconductor chip and substrate 14. Moreover, it should beunderstood that substrate 14 could be any type of substrate now known orlater developed. For example, substrate 14 could be ceramic or organic.In any event, interposer structure 16 is positioned betweensemiconductor chip 12 and substrate 14 under the present invention topreserve the interface therebetween. As indicated above, differences inthe CTE between semiconductor chip 12 (e.g., 3 ppm/° C., CTE) andsubstrate 14 (15-18 ppm/° C., CTE for an organic substrate) causevarious issues as semiconductor module 10 is subjected to temperaturechange. Positioning interposer structure 16 between semiconductor chip12 and substrate 14 increases the distance between the two componentsand alleviates the problems associated with the difference in CTEs.

In any event, interposer structure 16 generally comprises a elastomeric,compliant material 20 having metallurgical through connections 18“embedded” or “positioned” therein. Metallurgical through connections 18electrically connect under bump metallization (UBM) or bottom layermetallurgy (BLM) 22 of semiconductor chip 12 to top surface metallurgy(TSM) 24 of substrate 14. In a typical embodiment, interposer structure16 can comprise Cupil-T, which is commercially available from NittoDenko, Inc. of Osaka, Japan. Moreover, metallurgical through connections18 can be formed to have a predetermined shape depending on the loadapplied to semiconductor module 10 to best optimize the contact. Forexample, metallurgical through connections 18 could be spherical,ellipsoid, s-shaped, c-shaped, or elongate (i.e., column-like). variousfactors can be considered when determining the shape of metallurgicalthrough connections 18. Such factors include, among other things: (1)camber (i.e., non-flatness of substrate 14 and semiconductor chip 12) inthat more camber might mean taller through connections with an overallgreater degree of compressibility; (2) distortion (i.e., positionalaccuracy of the I/O pads on substrate 14) in that the worse thedistortion, the bigger the contact area on metallurgical throughconnections 18 that would have to be provided so that some degree ofcontact is always present between metallurgical through connections 18and the I/O pads; and (3) process considerations such as how the throughconnections are made. In addition, metallurgical through connections 18could be formed from one or more materials. To this extent,metallurgical through connections 18 could have a core formed fromCopper, Copper-Beryllium, or the like that is coated with gold. Stillyet, UBM 22 and/or TSM 24 could be gold, solder or the like.

To provide a more stable structure, interposer structure 16 could berigidly attached (e.g., hard soldered) to either UBM 22 or TSM 24, orboth. For example, if semiconductor module 10 is placed under a LandGrid Array (LGA) load, metallurgical through connections 18 could behard soldered to TSM 24, while the contact between metallurgical throughconnections 18 and UBM 22 is maintained solely by the LGA load. Thiswould enable free expansion of the semiconductor chip side of interposerstructure 16 under the influence of temperature. Since interposerstructure 16 would not cause any strains due to TCE mismatch, thereliability of semiconductor module 10 would increase considerably.Further, this method would allow for self-aligned solder joining ofmetallurgical through connections 18 to the I/O pads on substrate 14,thus eliminating the concern of inadequate surface contact area when theto pad distortion is on the high end of the specification.

Referring now to FIG. 2, semiconductor module 10 of FIG. 1 furtherincluding a heat spreader 26 and heat sink 30 is shown. As depicted,heat spreader 26 is attached to semiconductor chip 12 using thermallyconductive adhesive 28. To prevent the increased weight cause by heatspreader 26 and heat sink 30 from damaging semiconductor chip 12,substrate 14 and/or interposer structure 16, support posts 32A-B can beprovided adjacent to interposer structure 16. Specifically, supportposts 32A-B extend from substrate 14 to heat spreader 26, and supportheat spreader 26 over semiconductor chip 12. It should be appreciatedthat the quantity of support posts 32A-B shown in FIG. 2 is intended tobe illustrative only, and should not be limiting.

Regardless, to further seal interposer member 16 between semiconductorchip 12 and substrate 14, underfill could be provided. Specifically,referring to FIG. 3, semiconductor module 10 of FIG. 2 is shown asfurther including underfill 34. Under the present invention, underfill34 can be provided throughout the interconnection, or at predeterminedlocations. Further, underfill 34 can be a heat-curable material,selected from a broad range of chemical compositions including bothrigid and flexibilized thermosetting epoxies, thermoplastics, urethanes,polysulfones, polyimides, polyetheramides/imides, and hybrids of same.Alternatively, underfill 34 can be a more compliant, thermoplasticmaterial such as a silicone based product.

In any event, when underfill 34 is used, metallurgical throughconnections 18 could be rigidly attached to both UBM 22 and TSM 24 toprovide a desired level of thermo-mechanical fatigue. To this extent,underfill 34 may be applied between interposer structure 16 andsemiconductor chip 12, between interposer structure 16 and substrate 14,or between semiconductor chip 12 and substrate 14 (including interposerstructure 16). In a typical embodiment, it is desirable to rigidly affixinterposer structure 16 to substrate 14 whenever metallurgical throughconnections 18 are soldered to the substrate 14. In this case, atypical, high-modulus of elasticity underfill is indicated, e.g.,materials having modulus ranging from 1-10 Giga Pascals. Similarly, yetanother embodiment uses underfill 34 between semiconductor chip 12 andinterposer structure 16 if metallurgical through connections 18 arepermanently attached to the semiconductor chip 12.

In yet another embodiment of the invention, a more compliant, flexible,underfill material (having elastic modulus in the tens or hundreds ofMega Pascals, for example) is provided between the semiconductor chip 12and substrate, including metallurgical through connections 18. Thisfeature would allow lateral displacement of the electrical contacts inresponse to thermally-induced stresses while preserving environmentalprotection of the IC devices(s) and joints.

Referring now to FIG. 4, semiconductor module 10 of FIG. 3 under an LGAload is shown. Under an LGA load, forces are exerted on semiconductormodule 10 in the direction of the arrows shown. As indicated above inconjunction with FIG. 1, metallurgical through connections 18 could berigidly attached to TSM 24 under such a load. Referring to FIG. 5,semiconductor module 10 under a Temporary Chip Attachment (TCA)application is depicted. Under a TCA application, a porous surface isprovided for vacuum pickup and/or placement of semiconductor chip 10.Accordingly, as can be seen, interposer structure 16 can be used withinsemiconductor modules 10 in a variety of scenarios and applications. Inaddition, although not shown herein, interposer structure 16 could beused as a fan-out layer so that a very fine pitch in UBM 22 may beconnected to a more coarse pitch in substrate 14.

The foregoing description of the preferred embodiments of this inventionhas been presented for purposes of illustration and description. It isnot intended to be exhaustive or to limit the invention to the preciseform disclosed, and obviously, many modifications and variations arepossible. Such modifications and variations that may be apparent to aperson skilled in the art are intended to be included within the scopeof this invention as defined by the accompanying claims. For example, inanother embodiment, interposer structure 16 could be integrated at thewafer level (e.g., 8 or 12 inch wafers) and electrically tested beforechip singulation (e.g., dicing) is performed.

1. A temporary chip attachment structure, comprising: a semiconductorchip; a substrate; an interposer structure electrically connecting thesemiconductor chip to the substrate, wherein the interposer structureincludes metallurgical through connections having a predetermined shape;and a chip pick and place head adapted to one of pick up or place thesemiconductor chip.
 2. The temporary chip attachment structure of claim1, the chip pick and place head further comprising a vacuum system forpicking up the semiconductor chip.
 3. The temporary chip attachmentstructure of claim 2, the vacuum system further comprising a poroussurface on a side of the head adjacent the semiconductor chip.
 4. Thetemporary chip attachment structure of claim 1, the chip pick and placehead further comprising a cooling system configured to cool the head. 5.A temporary chip attachment structure, comprising: a semiconductor chiphaving an under bump metallization; a substrate having a top surfacemetallization; an interposer structure electrically connecting the underbump metallization to the top surface metallization, wherein theinterposer structure comprises an elastomeric, compliant material thatincludes metallurgical through connections having a predetermined shape;and a chip pick and place head including a vacuum chip pick-up.
 6. Thetemporary chip attachment structure of claim 5, the vacuum chip pick-upfurther comprising a porous surface on a side of the head adjacent thesemiconductor chip.
 7. The temporary chip attachment structure of claim5, the chip pick and place head further comprising a cooling systemconfigured to cool the head.
 8. A method for attaching a semiconductormodule, comprising: providing embedded metallurgical through connectionswithin an elastomeric, compliant material to form an interposerstructure; positioning the interposer structure between a semiconductorchip and a substrate to electrically connect the semiconductor chip tothe substrate; providing a chip pick and place head; and attaching thechip pick and place head to the semiconductor chip.
 9. The method ofclaim 8, the attaching further comprising using a vacuum system forpicking up the semiconductor chip.
 10. The method of claim 9, the vacuumsystem further comprising a porous surface on a side of the headadjacent the semiconductor chip.
 11. The method of claim 8, the chippick and place head further comprising a cooling system configured tocool the head.